1. Field of the Invention
The present invention relates to parity checking apparatus in general and in particular to parity checking apparatus which uses an auxiliary memory and an adaptive auxiliary memory addressing scheme to reduce the amount of memory required to-perform parity checking.
2. Description of the Related Art
The advent of personal computers ushered in by Apple Computer, IBM and other manufacturers has created a very large demand for memory chips in computers. With the introduction of Microsoft operating systems like Windows and Windows NT, the demand for memory capacity jumped from 1 megabyte to 4 megabytes for Windows applications, and to 8 or 16 megabytes for Windows NT applications. In the near future, a memory capacity of 32, 64 or even 256 megabytes is expected to be required for the more sophisticated operating systems.
To ensure the integrity of the data in a memory, one extra bit is added for each byte or 8 bits of data for parity checking. For a 32 bit data memory system, 4 more memory cells in addition to the 32 data memory cells are used to ensure 32 bit data memory integrity.
When each byte of data is written into the memory, a parity bit generator of the memory controller generates an odd or even parity bit. The choice of using odd or even parity is decided initially by the design engineer or subsequently by a user selectable jumper on the system board. Each generated parity bit corresponding to a byte of memory data is stored in an extra memory chip with a full address directly corresponding to the location of each byte of data in the memory chips. When each byte of data is read from the data memory, each corresponding parity bit is retrieved from the parity memory chip and is sent to a first input of a parity bit checker. In the meantime, the same parity bit generator in the same memory controller generates another new parity bit according to the incoming memory data. This newly generated parity bit is sent to a second input of the parity checker. The parity checker compares the retrieved parity bit with the newly generated parity bit. If the two bits match, the memory data is good. If the two bits do not match, the memory data is considered to be corrupted and a memory parity check is issued. The occurrence of a memory parity check causes the non-maskable interrupt (NMI) to halt the operation of the central processing unit (CPU). It is up to the user to either reset and restart the computer or have the computer repaired.
The additional memory chips for storing and retrieving the parity bits contributes approximately 11% to the cost of a memory. This seems to be trivial when memory capacity is at 1 megabyte. However, when memory capacity increases to 4 megabytes, 16 megabytes, 64 megabytes or 256 megabytes, the additional memory parity overhead cost can be extremely high. The following is a comparision of the cost of memory parity chips at present:
______________________________________ Memory chip of 1 megabyte by 1 $ 5 Memory chip of 4 megabytes by 1 $ 16 Memory chip of 16 megabytes by 1 $ 64 Memory chip of 64 megabytes by 1 $ 300 Memory chip of 256 megabytes by 1 $1200 (estimate) ______________________________________
From the foregoing list it can be seen that the additional memory parity overhead cost is considerable for memory capacities of 4 megabytes or more and becomes a very significant estimated $1200 per system when a 256 megabyte capacity is required. As a matter of fact, memory parity overhead cost can be four times more expensive for a computer with a 32 bit data bus like the Intel 486, and eight times more expensive for a computer with a 64 bit data bus like the Intel Pentium. This is because every 8 bits of memory data requires 1 additional memory cell for parity bit storage and retrieval. Thus a 32 bit system requires 4 additional memory cells, and a 64 bit system requires 8 additional memory cells.
This tremendous memory parity overhead cost for memory data integrity checking becomes extremely expensive especially when personal computers are becoming more like household commodity items. Since the volume of computer sales is estimated at 49 million units per year, and each computer is equipped with mostly 4 megabyte to 16 megabyte memories, the memory parity overhead cost is 49 million.multidot.(16+64)/2=$1.96 billion per year.
In view of the above-described memory parity overhead cost in some computer systems like the Apple Macintosh, the memory parity chips are eliminated completely in order to provide a cost saving. This can be very bad or even disastrous if the computer system is not able to check the memory data integrity during its operations. This is an even more serious problem when computers are used in business and industrial applications where large capacity memories are required, and detection of a memory failure is of the utmost importance for safe computer operation.
Therefore, there is a need for an improved low cost approach or alternative for the present memory parity checking system.